This invention relates to digital image processing in general, and more particularly, to an improved apparatus for processing frames of digitized information.
In operating on digitized image information, it is conventional to digitize frames of an image, e.g, a TV image into an array of pixels and store that array, the array, for example, being an array of 512.times.512 pixels. The digitized image may then be processed by combining the pixels in various mathematical or logic operations with other stored frames of information. Most prior art devices for doing this type of processing have done so at relatively low rates, off-line. However, there are applications, such as in medical diagnosis where on-line operation is extremely desirable. Furthermore, frame processors are called upon to do different functions. Information must be processed for interlacing and deinterlacing where conventional interlaced scan TV equipment is used. In other words, in processing, a deinterlaced frame is necessary. However, it may be received in an interlaced format and when again converted back to a video signal must be in an interlaced format for display on a conventional television screen. Frame processors must also do arithmetic and logic functions like addition and subtraction, in addition to being able to read and write information into a frame processor memory. Furthermore, there is a need for being able to carry out image intensity transformations in a frame processor. Although each of these functions could be separately built into different frame processors when needed in a system, there is a need for flexibility so that the same frame processor can be used to do any of these functions, either under hardware or software control.